ABSTRACT
This chapter addresses performance-driven interconnect synthesis, which seeks to optimize circuit performance by minimizing signal delays to critical sinks. It describes approaches that optimize Elmore delay directly while synthesizing a routing tree. Timing-driven wiring geometries are in general quite different from optimal-area interconnect trees, especially as die sizes continue to grow while feature dimensions steadily shrink. In parallel with these advances, sink-dependent delay objectives were recognized as more critical than net-dependent delay minimization. Because the timing-driven placement and routing design loop usually iterated tightly with static timing estimation, critical-path information was often available during routing. Objectives such as minimum tree cost, bounded radius, cost-radius trade-offs, and even arborescences were all motivated by analyses of the Elmore delay approximation. The initial tree construction procedure considers only Hanan grid points as candidate Steiner points. Adding extra wires to an existing routing tree can improve certain source–sink delays.
