ABSTRACT
This chapter presents buffer insertion in interconnect with a set of possible buffer positions and a discrete buffer library. Buffers can reduce wire delay by restoring signal strength, in particular, for long wires. The dramatic buffer scaling undoubtedly generates large and profound impact to very large scale integrated circuit design. Based on L. P. P. P. van Ginneken’s algorithm, numerous extensions have been made, such as handling of multiple buffer types, trade-off with power and cost, addressing slew rate and crosstalk noise, and using accurate delay models and speedup techniques. For a general case of signal nets, which may have multiple sinks, van Ginneken’s algorithm is perhaps the first systematic approach on buffer insertion. In addition to buffer insertion, wire sizing is an effective technique for improving interconnect performance. Noise avoidance techniques must become an integral part of the performance optimization environment.
