ABSTRACT
The growing dominance of global interconnects on circuit performance, it is desirable to optimize interconnects as early as possible. D. F. Wong and E. F. Young have also assumed the fixed interval buffer insertion constraint in their interconnect planning. This chapter presents the enabling concept of buffer planning, namely, the feasible region in which a buffer can be inserted such that the timing constraint is met. It summarizes several buffer planning methodologies that tackle the design challenges brought forth by the exponential growth of buffers. For buffer site planning, we shall plan for the buffers during/after floorplanning such that the given buffer sites can accommodate buffers and the routing timing and congestion constraints are satisfied. There are two approaches to buffer planning: buffer block planning and buffer site planning. The locations of buffer blocks/sites are places where signals get in and out and it is thus essential to consider routability and buffer planning simultaneously.
