ABSTRACT
This chapter discusses basic concepts and techniques for deep submicron power grid design and verification in various aspects: modeling, methodology, analysis, and optimization. It also discusses widely adopted power grid analysis and verification methodologies and modeling for every part of the power distribution system. The chapter addresses four analysis techniques to handle large-scale power grid circuits with fixed and uncertain work loads: Optimization techniques including wire sizing, decoupling capacitance optimization, topology optimization, and optimal power pads/pin placement. The annual report of the International Technology Roadmap for semiconductors has shown the continued reduction of power supply voltage, driven by power consumption reduction, reduced transistor channel length, and reliability of gate dielectrics. Realistic power grid analysis methodologies must handle cells or power grids in a hierarchical manner to manage the complexity of the problem. For static analysis, the maximum voltage drop among all power grid nodes is a general metric for the entire chip.
