ABSTRACT
This chapter discusses the stage by describing the architecture of Field-programmable gate arrays (FPGAs). It describes several programming technologies. The chapter also describes logic block architectures. It examines routing architecture and also discusses embedded memories and embedded computation blocks. The tracks are connected to each other and to the logic blocks using programmable switches. Commercial FPGAs often contain combined switch blocks and connection blocks, however for clarity, this section will describe each separately. Therefore, Flash-based FPGAs have a slower time-to-market compared to the static random access memory-based FPGAs. Distributed memory, on the other hand, uses small memories spread across the entire FPGA chip, often implemented in unused logic elements. To support applications involving microcontrollers and microprocessors, FPGA manufacturers offer embedded processors tailored to interface with the FPGA logic fabric. Switches in modern FPGAs are typically buffered, because unbuffered switches result in a quadratic increase in delay for long connections.
