ABSTRACT

The search for alternative high-κ dielectrics to replace thermally grown SiO2 and Si oxynitride alloys as gate dielectrics in aggressively scaled Si complementary metal oxide semiconductor (CMOS) devices has focused on transition metal and lanthanide rare earth oxides and their respective silicate and aluminate alloys [1]. There are several factors that must be considered to make these replacements possible; these are based on more than 20 years of increases in integration, and the accompanying decreases in lateral dimensions and oxide physical and equivalent thickness in SiO2 dielectrics. First, there must be significant reductions in direct tunnelling at operating bias levels by at least three to four orders of magnitude with respect to SiO2 as the equivalent oxide thickness (EOT) is reduced to 1.0 nm and below. Additionally, the channel mobilities of electrons and holes must be approximately 90% of their values in SiO2 devices. Finally, other device performance and reliability metrics must be essentially the same as SiO2, which means that (i) interfacial and bulk defect densities such as interfacial traps, D it, and fixed charge, Q f, must be < 1011 cm−2 and (ii) defect generation under accelerated stress bias testing must correspond to times to failure of about 10 years. In addition, there are many other issues relating to process integration; paramount among these are issues related to the stability 326of alternative dielectrics against chemical phase separation and/or crystallization below temperatures required for down-stream process steps including dopant activation in source and drain contacts at temperatures ∽ 900–1000°C. Other process integration issues include the eventual substitution of a pair of metal gate electrodes with Fermi level energies respectively equivalent to those of n + and p + doped polycrystalline Si. This integration issue will not be addressed in this chapter, although issues related to chemical bonding and stability at the interfaces between alternative dielectrics and metal gates are at least as challenging as those at the crystalline Si–dielectric interface that is one of the focal points of the chapter.