ABSTRACT
The increasing heterogeneity and programmability associated with system-on-chip (SoC) architecture, together with ever-increasing operating frequencies and technology changes, are demanding fundamental changes in integrated circuit (IC) testing. At-speed testing of high-speed circuits with external testers is becoming increasingly difficult owing to the growing gap between design and tester performance, the growing cost of high-performance testers, and the increasing yield loss caused by inherent tester inaccuracy. Therefore, empowering the chip to test itself seems like a sensible solution. Hardware-based self-testing techniques (known as built-in self test, or BIST) have limitations owing to performance, area, and design time overhead, as well as problems caused by the application of nonfunctional patterns (which may result in higher power consumption during testing, over-testing, yield loss problems, etc).
