ABSTRACT
CONTENTS 17.1 Introduction ...................................................................................................................... 497 17.2 Stress-Induced Leakage Current.................................................................................... 499
17.2.1 SILC Phenomenology......................................................................................... 500 17.2.2 SILC Growth with Stress Level ........................................................................ 501 17.2.3 Origin of Defects Leading to SILC ................................................................... 503 17.2.4 Microbreakdown................................................................................................. 504 17.2.5 SILC in Tunnel Oxides....................................................................................... 504
17.3 Ionizing Radiation Effects in Thin Oxides ................................................................... 508 17.3.1 Radiation-A Concern for Harsh Environments Only ................................. 508 17.3.2 Two Broad Classes of Ionizing Radiation Effects .......................................... 509
17.4 RILC in Ultrathin Oxides................................................................................................ 511 17.4.1 RILC Model ......................................................................................................... 511 17.4.2 RILC Dependence on Applied Bias during Irradiation ................................ 513 17.4.3 Radiation versus Electrical Stress ..................................................................... 515
17.5 RILC in Tunnel Oxides ................................................................................................... 517 17.5.1 Physical Characteristics of the RILC Path....................................................... 519 17.5.2 Model.................................................................................................................... 520 17.5.3 RILC in Thin versus Thick Oxides ................................................................... 522 17.5.4 Erratic Behavior of RILC.................................................................................... 523
17.6 Summary and Conclusions ............................................................................................ 526 Acknowledgments ..................................................................................................................... 527 References.................................................................................................................................... 528
The first studies on metal-oxide-semiconductor (MOS) structures date back to the 1960s, and several years were spent in research before the first complementary MOS (CMOS) was introduced in 1968 [1] by integrating both nMOS and pMOS in the same chip, thus allowing high-speed and very low power dissipation. Since then, silicon integrated circuits have penetrated into virtually every apparatus with electrical components. The key of the technology growth [2] has been the drive to smaller and smaller dimensions using the principle of scaling [3]. MOSFET scaling-down is based on the idea of changing device
over last 10-15 years the operating electric field has been maintained around E¼ 5 MV=cm in the oxide (constant-electric-field scaling), as dictated by transistor reliability, which is dominated by time-dependent dielectric breakdown (TDDB) [4,5] (Chapters 15 and 16), channel hot-carrier injection (CHC) [5,6], and other degradation phenomena such as negative bias temperature instability (NBTI) [7,8] (Chapters 12 through 14). Scaling the gate oxide and channel length by a factor k allows designers to increase the device density by a factor k2 due to the smaller wiring and device dimensions, improves the speed thanks to a k gain in the transconductance-to-capacitance ratio (gm=C), and reduces the power dissipation by a factor k2 because of the reduced voltage and current in each device, while keeping control over short-channel effects. However, the voltage is actually scaling slower than device physical dimensions. More importantly, the oxide is becoming thinner and thinner, and reaching its ultimate physical limits. Now gate oxides in modern state-of-theart technologies are so thin (1-2 nm) that leakage current due to direct tunneling is a major issue [9]. New materials such as aluminum or hafnium oxides, having a larger dielectric constant in comparison to SiO2, have been studied to replace silicon dioxide as the gate dielectric in the last several years [10] (Chapters 9 through 11), and are finally entering mass production [11], at least for high-end applications. Some high-k dielectric materials are already in use in devices such as dynamic random-access memories (DRAMs) [12]. The advantage of having a high-k material is that the same equivalent electrical thickness (i.e., the same capability to control short-channel effects) is obtained with a larger physical thickness (hence, lower tunnel current). Despite the advancement of such technologies, SiO2 is still the workhorse gate dielectric of the semiconductor industry, and is expected to retain its role for several years. In fact, high-kmaterials are difficult to integrate into the CMOS process flow [13], requiring complex process changes such as suitable gate replacements [11]. For this reason, even state-of-the-art technologies may be realized without using them at all [14]. In this chapter, we will review the reliability of thin and ultrathin oxides. We will
discuss SiO2 only, because of its ubiquity and the huge amount of literature on this subject. Silicon nitridation [15,16] is routinely used to prevent boron penetration in the gate oxide. The use of nitrided oxides (briefly, SiON) slightly enhances the dielectric constant of the dielectric, thus helping to reduce direct tunneling currents, but may also result in enhanced degradation of the oxides [8,17]. Since nitridation is performed in various measures in all modern technologies, we will not distinguish between nitrided or nonnitrided oxides, speaking simply of SiO2 (unless otherwise stated). Furthermore, we will focus on the degradation of the insulating properties of the oxide due to two different causes. At first, we will consider high-field electrical stress, which is encountered during actual operation for some classes of devices (such as the tunnel oxide of nonvolatile memories) and used to simulate the long-term degradation for others (thin gate oxides in advanced logic devices). Then, we will review the loss of insulating properties due to ionizing radiation. Once again, this will be done for the two classes of oxide thicknesses previously mentioned. We will generally use ‘‘gate oxide’’ to refer to the gate dielectric of an aggressively scaled metal-oxide-semiconductor field-effect transistor (MOSFET), which varies with thickness and nitride concentration, depending on the technology node (a 5 nm oxide in a 0.25 mm long transistor actually was aggressively scaled just a few years ago), and ‘‘tunnel oxide’’ to refer to the dielectric separating the floating gate from the substrate in nonvolatile memories (as we will discuss later, the thickness of this oxide is not scaling at all with the technology due to reliability constrains). In this chapter, we will not cover catastrophic phenomena induced by electrical stress
such as breakdown or soft breakdown (SB) [18,19]; these topics are covered in Chapters 15
radiation such as single event gate rupture (SEGR) [20,21], that is, the catastrophic breakdown following the impact of a single, high-energy ion on a biased oxide.
