ABSTRACT
CONTENTS 3.1 Introduction .......................................................................................................................... 57 3.2 State of the Art: Strained-Si MOSFETs............................................................................. 57 3.3 Yield of Integrated Circuits ................................................................................................ 58 3.4 Defects in Strained Layers .................................................................................................. 61 3.5 Strained-Layer Critical Thickness and Strain Relaxation .............................................. 64 3.6 Process Flow ......................................................................................................................... 65 3.7 Strain and Alternative Wafer Orientation........................................................................ 67 References...................................................................................................................................... 67
Strained-Si channel metal-oxide-semiconductor field-effect transistors (MOSFETs) are used in nearly all 90 nm and smaller commercial logic technologies. Strained channels improve the electron and hole motilities by altering the semiconductor band structure. Strained semiconductor layers are known to produce dislocation defects and have been extensively studied on blanket wafers on which several materials science review papers have recently been published [1-4]. However, much less has been published on strained-Si defects relating to manufacturing commercial production technologies which we address in this chapter. The chapter is outlined as follows: Section 3.2 briefly reviews strained-Si MOSFETs in state-of-the-art production technologies, Section 3.3 covers the yield of integrated circuits, Section 3.4 focuses on defects in strained-Si layers, Section 3.5 discusses strain relaxation, Section 3.6 describes process flow thermal cycles and manufacturing tradeoffs, and Section 3.7 briefly introduces the potential benefits and problems involving incorporating strain in alternative wafer orientations.
