ABSTRACT
We analyze the operation of a semiconductor-nanowire based memory cell. Large changes in the nanowire conductance result when the magnetization of a periodic array of nanoscale magnetic gates, which comprise the other key component of the memory cell, is switched between distinct configurations by an external magnetic field. The resulting conductance change provides the basis for a robust memory effect, which can be implemented in a planar semiconductor structure consistent with conventional integrated-circuit architectures.
