ABSTRACT
The term systolic arrays was coined by Kung and Leiserson in 1978 to describe application specific VLSI architectures that were regular, locally connected and massively parallel with simple processing elements (PEs). The idea of using such regular circuits was even present in von Neuman’s cellular automata in the fifties, Hennie’s iterative logic arrays in the sixties, and also in specialized arithmetic circuits (Lyon’s bit-serial multiplier [1] is clearly a linear systolic array). However, the emergence of VLSI technology in the late seventies and early eighties made the time ripe for introducing such architectures in order to highlight the characteristics appropriate to the technology.
