ABSTRACT
The network topology is a key factor for the performance and cost of any Network-on-Chip (NoC) design. As anticipated in Chapter 1, the actual trend for chip multiprocessors is to choose a 2-D mesh because of its regularity, its suitability for the bidimensional silicon surface, and for the better predictability of its electrical parameters. However, as the number of end nodes in future on-chip networks increases, this might not be the best choice, since the 2-D mesh is well-known to incur bandwidth and latency scalability issues.
