ABSTRACT
Contents 1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 Low-Power Design for Embedded Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.3 The Role of On-Chip Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.4 Optimization of the Energy Consumption of the Memory
Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.4.1 Hierarchical memory architectures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.4.2 A practical example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.5 The Goal and Organization of the Book . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Digital systems had initially only one main design metric: performance. Other cost parameters such as area, energy consumption, or testability were regarded as design constraints. In the early nineties, the role of power consumption changed from that of a design constraint to an actual design metric. This shift occurred due to technological reasons: higher integration and higher frequencies led to a significant increase in power consumption.1
