ABSTRACT
Extensive past research for improving microprocessor performance and power has focused on the instruction cache due to the cache’s large impact on those design factors. Proposed optimization techniques typically exploit an instruction stream’s spatial and temporal locality. Popular techniques include prefetching, victim buffers [64], filter caches [29,36], loop caches [22,25,38], code compression [9], cache tuning [6,23,27,65,66], and code reordering [34,47].
