ABSTRACT
The need o f the semiconductor industry to increase the signal transmission speed beyond the present limit of 300 MHz requires faster transmission lines. This is because the overall speed o f large, high-density chips is presently not limited by the transistor speed but, rather, by the on-chip circuits that connect them1. Specifically, the resistance (R) o f the conductors and the capacitance (C) of the insulators cause what is known as an “RC” time delay, which limits the chip speed when it is larger than the inherent switching time of the transistor. The goal o f the
microelectronics industry o f reducing the RC time delay must be achieved for smaller dimensions and larger die sizes. This is a difficult challenge, for interconnects with smaller cross sections have higher resistances, as do the longer lines found in larger dies. Further, thinner dielectrics have higher capacitances. Thus, one is limited to any o f three ways to reduce the RC delay time: (1) decrease R by using a higher conductivity metal, (2) decrease C by using dielectrics having lower dielectric constants and (3) decrease the length o f the metal lines by using multilevel interconnect devices.
