ABSTRACT
The dominance of silicon CMOS devices in digital applications and their increasing penetration in analog applications imply that any commercial-off-the-shelf technology used in extreme environments will include a large number of CMOS devices performing critical functions. It is therefore important to understand and predict the behavior of CMOS devices in extreme environments. Exposure of CMOS devices to cryogenic temperatures results in an improvement in a number of key device metrics. The off-state current in CMOS devices has traditionally been dominated by the subthreshold drain-to-source current. Device matching is an important metric that determines the performance of many critical analog circuit blocks such as differential pairs, current mirrors, bandgap references, and feedback networks. The effects of interface traps on the matching performance of scaled MOSFETs operating in weak inversion have been demonstrated. These results raise important new issues that need to be addressed for reliable operation of scaled MOSFETs in extreme environment applications.
