Considerations for the Reliability Estimation of Silicon CMOS

The reliability models generated for the base technologies will adequately predict integrated SiGe parameter shifts and estimated lifetimes. This chapter presents some additional complementary metal-oxide-semiconductor (CMOS) reliability considerations and methodologies that can be applied under extreme operating environments for the “gradual” shift CMOS mechanisms. Since the hot carrier mechanism in CMOS requires drain current as well as a high V_DS, normal CMOS switching operation will incur significant degradation only during the relatively short switching transients. HC and bias temperature instability cause gradual and collective CMOS circuit degradation. Negative bias temperature instability (NBTI) has been a well-known degradation mechanism for some time for SiO₂ dielectrics. When the gate dielectric processes began to incorporate nitrogen, the mechanism became worse. NBTI is only a concern in p-MOSFETs.