ABSTRACT
The high-temperature electronics market is widely considered one
of the main areas for silicon-on-insulator (SOI) device applications.
In the last decade, integrated circuit technology advanced towards
the deep submicron era to improve device performance, lower
power consumption, reduce die area, etc. This unavoidably resulted
in the appearance of new physical phenomena and/or significant
changes to existing ones. Indeed, progress in technology does not
mean simply device shortening, which is directly related to gate
oxide thinning, doping level change or introduction of high-k/metal gate stacks, but at the same time requests the introduction of new
architectural solutions for the control of short-channel effects (SCE),
such as various multiple-gates devices.
