ABSTRACT
The continuous gate oxide thickness reduction brings the gate stacks
to the limit of several atomic layers of dielectric, which causes
a dramatic increase in gate tunneling leakage. This gate leakage
degradation can be limited by considering gate dielectrics with
a higher relative permittivity than SiO2. In this context, original
architectures like the Multiple Gate FETs (MuGFETs) can help to
put less stringent requirements on the high-k dielectric thickness. In these devices, better channel confinement is obtained by
encapsulating the silicon film between two or more gates. Excellent
Short Channel Effect control is achieved by reducing the distance
between the gates (i.e., thinning the Si film). Therefore, the Short
Channel Effect control can be maintained without having to invest
considerable effort in thinning the gate dielectric [Lee et al. (2007)]. The first section of this chapter covers the processing of high-k
dielectrics/metal gate electrodes on fully depleted MuGFETs on SOI.
The goal is to determine to which extent the integration of such
electrodes can help meeting ITRS requirements. A description of
the gate stack processing is also provided. The second section is
dedicated to several methods used for controlling and tuning the
work function in MuGFETs with metal gates. In the last section of
this chapter a method for work function extraction on SOI MuGFETs
is presented. The latter is able to cope simultaneously with the
presence of high-k dielectrics and the absence of a bulk contact (SOI). This approach relies on the universality of the dependence
between the band structure of a MOSFET and its gate tunneling
leakage response.
