ABSTRACT
In spite of massive efforts and investment within the semiconductor
industry, gate length scaling has slowedwith respect to the demands
set out in the ITRS roadmap [1]. This is largely because the gate
dielectric thickness has not scaled fast enough. For high perfor-
mance microprocessor applications this has resulted in severe
issues with active power dissipation as the supply voltage cannot
be reduced unless the oxide is also scaled. For mobile applications,
the other major CMOS technology driver, the poorer gate control of
the channel and increased gate leakage has led to an explosion in
off-state leakage current levels that severely limit battery life.
