ABSTRACT
While traditional scaling used to be accompanied by an improve-
ment in device performance, this is much more challenging in
sub-100 nm technology generations, causing an inefficient scaling
of transistor dimensions and circuit supply voltage. Leakage and
variability in devices approaching the atomic scale are major
limiting factors for continued employment of conventional CMOS
technology. Three-dimensional architectures ensuring a tighter
electrostatic control over the channel have potential to mitigate
the outlined issues. By choosing a proper combination of high-κ
and metallic materials for the gate stack, it is possible to (i)
resume a healthy trend of channel length scaling, (ii) limit gate
leakage and (iii) set the device threshold voltage without recurring
to increased channel doping. The use of undoped channels in
multiple-gate structures such as FinFET significantly reduces the
impact of random dopant fluctuations, which represent the major
contribution to variability in planar bulk architectures. On the
other hand, increased process complexity due to the intrinsic 3D
nature of FinFETs is reflected in a significant impact of geometry
fluctuations. Line-edge roughness (LER) of the fin, top-and sidewall-
gates is expected to be the dominant source of fluctuations in these
devices.
