ABSTRACT
This chapter presents some noise-shaping, noise-canceling techniques at front end and baseband, focusing particularly on frequency dependent negative resistance-based noise-shaping filtering techniques in a 65 nm complementary metal oxide semiconductor (CMOS) process. The most critical block in the design is the first stage low noise amplifier, which generally sets the performance of the radio. Current-mode noise-shaping filtering has as well been proven to another low noise, low distortion filtering technique that is suitable for wireless communication applications. In the case of a gain-filtering interleaved architecture, the design of the first amplifier stage can still be demanding. A design covering a tuning range from 700 kHz to 5.2 MHz is fabricated in a 65 nm CMOS process and tested. With an increasing demand for wireless/mobile applications, deep, submicron CMOS has become a very attractive platform to design SOC radios for the emerging standards.
