ABSTRACT
The relentless scaling of complementary metal-oxide-
semiconductor (CMOS) transistors, tracked by the International
Technology Roadmap for Semiconductors (ITRS) and captured in
the famous Moore’s law, has driven the phenomenal success of the
semiconductor industry, delivering larger, faster, cheaper circuits.
Silicon technology has entered the nano-CMOS era with 30 nm
metal-oxide-semiconductor field-effect transistors (MOSFETs) in
mass production at the current 32/28 nm technology generation
and sub-10 nm transistors expected to enter mass production
shortly after 2020. A handful of dopants (10-20 altogether) will
control the characteristics of such nanoscaled transistors. Current
fabrication technologies result in random numbers and positions
of dopants in the corresponding transistor, architectures, creating
significant variability in their characteristics. This has become
already one of the fundamental limits of CMOS scaling and
integration. Indeed, random dopant fluctuations prevent the scaling
of the conventional bulk MOSFETs beyond the 20 nm gate length
mark and have driven the introduction of FinFETs, which tolerate
low channel doping and hence reduce the statistical variability,
at the 22 nm CMOS technology generation. This has sparked
the “transistors war” between FinFETs and fully depleted silicon-
on-insulator (FD SOI) transistors, both offering almost identical
remedies to the random dopant problem. Extending the scaling to
around the 10 nm gate length mark, the introduction of FinFETs
and FD SOI transistors has shifted the problem of random dopant-
induced variability from the channel to the source-drain regions of
the transistors.
