ABSTRACT
Downscaling has been the leading paradigm of the semiconductor
industry ever since the invention of the first transistor in 1947
[1]. Miniaturization of the single most important building block of
modern silicon-based electronic devices-the field-effect transistor
(FET)—has advanced to a stage where device performance depends
on the number and discrete distribution of individual dopants [2]
as channel lengths approach the 10 nm scale [3]. Consequently,
the ability to control dopant density and distribution on a sub-
nanometer level is a key challenge for further scaling of conventional
integrated nanoelectronic devices. The realization that “traditional”
miniaturization of conventional silicon devices by geometric scaling
will soon reach its ultimate limit (set by the discreteness of matter)
has led to intensified research in alternative approaches to further
enhance the computational power of logic devices.
