Bottom-Up Approaches for CMOS Scaling in the Nanoscale Era

Feature sizes in complementary metal–oxide–semiconductor (CMOS) technologies have been scaled from 3 μm to sub-nanometers using the "top-down" scaling techniques. This chapter describes the potential applications of metalloporphyrin self-assembled monolayers (SAMs) in nano-CMOS scaling and in modifying electronic properties of graphene field effect transistors (FETs). It explains the bottom-up approaches for CMOS scaling in the nanoscale era. The chapter disscusses a few issues related to CMOS scaling. Miniaturization of CMOS devices has major advantages like increased processing power, higher transistor density, and reduced cost per transistor. The chapter also discusses the applications of porphyrin SAMs as copper diffusion barriers, for gate electrode work function tuning, and in modifying the electronic properties of graphene FETs. Porphyrin SAMs as Copper Diffusion Barriers presents the application of zinc–porphyrin SAMs as copper (Cu) diffusion barriers for advanced back-end CMOS technologies. The SAM layers are integrated with various inter-layer dielectrics such as SiO₂, hydrogen silsesquioxane, and black diamond.