ABSTRACT
This chapter presents the design of static random access memory (SRAM) cells in carbon nanotube field-effect transistors (CNTFETs) technology. It provides a brief description of both standard six-transistor SRAM and a decoupled read and write eight-transistor SRAM. SRAM is a major component of digital systems such as microprocessors, reconfigurable hardware, and field programmable gate arrays, just to name a few. Building a large memory out of SRAM cells in the presence of metallic CNTs requires a fault-tolerant scheme to overcome faulty memory cells. The chapter also presents performance of CNTFET memory cells without metallic carbon nanotubes (CNTs). It focuses on the performance and parameter variation influences on CNTFET memory cells. The chapter shows that the metallic-CNT-tolerant technology and its influence on memory design. It evaluates and optimizes the proposed cell design for both performance and functionality. The chapter discusses memory module and spare column schemes. It also discusses the influence of technology scaling.
