ABSTRACT
Nanotechnology enables future advancements in integrated circuitry's miniaturization, energy and cost efficiency, and capabilities. However, a popular, chemically assembled electronic nanotechnology (CAEN) has a high rate of defects that negates these benefits of the nanofabric. The CAEN built-in self-test approach configures a nanoblock as a tester to test its neighboring nanoblocks. This chapter discusses a testing methodology for nanofabric systems that configures the components as block under tests (BUT) and comparators. It introduces an optimization technique, which can increase both the testing speed and the usability (yield) of the nanoblock. The chapter presents the basic concept of the nanofabric-based digital circuits. It discusses an example application of the self-test procedure in the context of a reconfigurable digital logic design. A defect map is generated to aid logic function implementation in a nanofabric. The chapter explains the design of the BUT configurations for the targeted faults.
