ABSTRACT
This chapter provides a brief review of low-power Full adders (FAs). Many low-power FA designs based on pass-transistor logic have been proposed. FA cells are used in many arithmetic operations and are crucial in both central and floating-point units. In general, the pass-transistor FAs have fewer gates/transistors and achieve lower power consumption. The chapter details several different FAs based on XOR–XNOR gates. It presents the effect of the transistor sizing on VTH variations. The single VTH loss of the complementary and level restoring carry logic FA design should enable it to function at lower supply voltages. Simulations were performed to study the effect of using the optimal sizing method on the performance, the power consumption, and the reliability of two FA cells: the standard mirrored 28T FA and the Test group FA. A comparison between the classical and optimal-sized FAs at the same supply voltage shows that the optimally sized ones consume more power than the classical counterparts.
