ABSTRACT
This chapter presents two approaches for efficient timing-aware transition fault pattern generation that provides higher small-delay defects (SDDs) coverage with a reasonable increase in the number of test patterns. In both approaches, a subset of transition faults is identified that should be targeted by the timing-aware Automatic test pattern generation (ATPG); for the rest of the faults, classic non-timing-aware transition fault patterns can be generated. As only a fraction of faults is considered for timing-aware ATPG, the proposed approaches also result in runtime savings. The first approach has an advantage of higher Delay test coverage (DTC); the pattern count for the second approach is lower compared to the first method. For several industrial circuits, a comparative analysis of existing and proposed methods of generating timing-aware test patterns for SDDs is presented. The presented approaches require little or no modification in the existing commercial ATPG and achieve better or similar results compared to existing timing-aware ATPG approaches.
