ABSTRACT
Process variation and noise can result in the longest path through a gate varying from chip to chip or across operating conditions. Therefore, testing only one path through each gate cannot guarantee the detection of the smallest local delay faults. Testing the K longest paths through a fault site increases the fault detection probability. If the extended partial path is not a complete path, some false path elimination techniques are applied to it to more efficiently prevent the new partial path from becoming a false path. Then, the min-max esperance of the partial path is updated, and it is inserted into the path store. The path generation iteration stops when K longest testable paths through gate are found or the path store is empty. Since the K longest testable paths through different gates may overlap, every time a new path is generated.
