ABSTRACT
This chapter presents a novel pattern evaluation and selection procedure that results in high-quality tests for screening small-delay defects (SDDs). From the implementation of the proposed procedure on several benchmarks, this procedure can result in a pattern count as low as a traditional 1-detect pattern set and long-path sensitization and SDD detection similar to or even better than the N-detect or timing-aware pattern set. This procedure is capable of adding important design parameters, such as process variations, cross talk, power supply noise, and the like. The chapter processes variations and cross talk that are added in the pattern evaluation and selection procedure. It is assumed that delay variations on path segments were independent from each other. It was seen that the mean and variance of the delay of each path segment were bounded. There are millions of interconnect segments running in parallel in a design, with parasitic coupling capacitances between them, introducing crosstalk effects and the circuit delay.
