ABSTRACT
The continuous increasing performance of microelectronics prod-
ucts places a high demand on packaging technologies. Higher func-
tionalities, high miniaturization, high reliability and low production
cost are the main drivers, and the requirements are driven by the
consumer market. On one hand, when components are integrated
into one package as an electronic system, the arrangement is called
“system in package” (SiP). On the other hand, when functionality
and integration level are directly connected with the core CMOS,
the arrangement is labeled “system on chip” (SoC). In SiP, different
technologies are used to meet specific needs. One of the most
promising approaches is 3D integration. This technology involves
several developments, including stacked devices or packages, a
silicon interposer with through-silicon vias (TSVs) and embedded
technologies.
