ABSTRACT
For the development of Application Specific Integrated Circuits (ASICs) for safety-related applications, Hardware Description Languages (HDLs) are used. The process of such development is presented in the international standard IEC 61508, which introduces guidelines and calculations to achieve a specific Safety Integrity Level (SIL). However, it is not concerning the estimation and calculation of the reliability of used HDL codes. In this paper, an overview of the novel reliability model for the quantitative evaluation of the reliability of HDL Designs is introduced. Based thereon, a practical application of the presented reliability model is shown. An example of the quantitative reliability calculation of the digital circuit design is described with the inclusion of multiple errors within a failure to validate the new approach of the reliability model for HDL. For this, conventional Software Reliability Models (SRMs) are applied. Due to the parallel processing nature of HDL more concurrent faults can lead to a failure, therefore current SRMs need to be extended. Specifically, the comparison between the Classical Programming Languages (CPL) based on a single error, and the HDL description with the multiple errors are represented. The results of the CPL and HDL are analyzed according to the differences, which are caused by the approach of the adaptation of the SRMs. Reliability corruption that results from the calculation of the single error is corrected by the multiple errors for the HDL. This allows the validation of the new approach of the reliability model of HDL with the existing SRMs of CPL. For the execution of test cases, Field Programmable Gate Arrays (FPGAs) are useful as a prototyping platform. Through the test cases, failures are detected in the FPGA, which are configured with the hardware function of the target HDL code.
