ABSTRACT
In all semiconductor memories, static random access memory (SRAM) is with the closest device structure to the conventional devices and is most representative of the VLSI technology. Compared to other types of memory cells, the design and optimization of SRAM cell is an unavoidable task and strongly associated to more general issues in the technology development. Among all process-induced variables, gate length is dominant. Besides physical gate length edge roughness caused by litho resist and reactive ion etch, variation of effective gate length is also caused by spacer, extension and source/drain implant, and rapid thermal anneals. Channel doping is another dominant variable in small devices and is mainly driven by well and halo implantation. The major outcome is random doping fluctuations of threshold voltages and drive currents, which is inversely proportional to the effective transistor channel area. To extract the correlations between each primary response and process-induced variables, one has to decouple the process-induced variables.
