Skip to main content
Taylor & Francis Group Logo
    Advanced Search

    Click here to search products using title name,author name and keywords.

    • Login
    • Hi, User  
      • Your Account
      • Logout
      Advanced Search

      Click here to search products using title name,author name and keywords.

      Breadcrumbs Section. Click here to navigate to respective pages.

      Chapter

      FinFETs
      loading

      Chapter

      FinFETs

      DOI link for FinFETs

      FinFETs book

      Designing for New Logic Technology

      FinFETs

      DOI link for FinFETs

      FinFETs book

      Designing for New Logic Technology
      ByWitek P. Maszara
      BookMicro- and Nanoelectronics

      Click here to navigate to parent product.

      Edition 1st Edition
      First Published 2015
      Imprint CRC Press
      Pages 24
      eBook ISBN 9781315215457
      Share
      Share

      ABSTRACT

      This chapter uses the term finfield-effect transistors (FinFET) to describe a transistor with a fin-shaped three-dimensional body whose height is several times greater than its width. It discusses the Fin shape, pitch, isolation, doping, crystallographic orientation, and stressing, as well as device parasitics, performance, and patterning approaches. Implementation of high-mobility materials for FinFET devices is briefly reviewed, as well as design challenges for logic and smaller static random-access memory (SRAM) circuits. SRAM design with FinFETs requires optimization for securing stable operation with the minimum number of fins in its one-fin pull-up transistor, one-fin pass-gate transistor and one-fin pull-down transistor device types for a small SRAM footprint. FinFET devices deliver much-improved short-channel control through their fully depleted operation and require low or no doping in the channel. FinFETs have inherently higher parasitic capacitance than corresponding planar devices. FinFET technology faced two key barriers to their implementation in products: demanding process integration and its significant impact on layout and circuit design methodology.

      T&F logoTaylor & Francis Group logo
      • Policies
        • Privacy Policy
        • Terms & Conditions
        • Cookie Policy
        • Privacy Policy
        • Terms & Conditions
        • Cookie Policy
      • Journals
        • Taylor & Francis Online
        • CogentOA
        • Taylor & Francis Online
        • CogentOA
      • Corporate
        • Taylor & Francis Group
        • Taylor & Francis Group
        • Taylor & Francis Group
        • Taylor & Francis Group
      • Help & Contact
        • Students/Researchers
        • Librarians/Institutions
        • Students/Researchers
        • Librarians/Institutions
      • Connect with us

      Connect with us

      Registered in England & Wales No. 3099067
      5 Howick Place | London | SW1P 1WG © 2022 Informa UK Limited