This chapter uses the term finfield-effect transistors (FinFET) to describe a transistor with a fin-shaped three-dimensional body whose height is several times greater than its width. It discusses the Fin shape, pitch, isolation, doping, crystallographic orientation, and stressing, as well as device parasitics, performance, and patterning approaches. Implementation of high-mobility materials for FinFET devices is briefly reviewed, as well as design challenges for logic and smaller static random-access memory (SRAM) circuits. SRAM design with FinFETs requires optimization for securing stable operation with the minimum number of fins in its one-fin pull-up transistor, one-fin pass-gate transistor and one-fin pull-down transistor device types for a small SRAM footprint. FinFET devices deliver much-improved short-channel control through their fully depleted operation and require low or no doping in the channel. FinFETs have inherently higher parasitic capacitance than corresponding planar devices. FinFET technology faced two key barriers to their implementation in products: demanding process integration and its significant impact on layout and circuit design methodology.