ABSTRACT
As CMOS technology is scaled down, leakage power is predicted to become dominant than dynamic power. Especially, in sub-100-nm technologies, the dynamic power is no longer the dominant contribution to the chip power consumption, because of the much faster increase of the leakage power at each technology generation. For example, at the 65-nm technology node, the leakage power is in the order of half the chip power consumption and is planned to be an even greater fraction in successive technologies [8]. Hence, the leakage power can be easily measured in the traditional power analysis attacks. Nowadays, leakage power analysis attacks which are another type of power analysis attack are reported and analyzed. Due to the strong leakage dependence on the input digital circuits [9], leakage power can also provide a significant amount of information on the secret key. Literature in [10] [11] proposed leakage power analysis attack which is a novel class of attacks to nanometer cryptographic circuits. Leakage power analysis attacks are recently shown to be a new serious threat to information security of smart cards.
