ABSTRACT
The input stage is consist of complementary dierential input pair, constant gm circuit, and a bias circuit. M1, M2 and M3, M4 respectively composed of NMOS, PMOS input pair, and M1 ~ M4 form complementary input dierential pair. M5, M6 are current switch, M9, M10 and M11, M12 are respectively composed of two 1: 3 Current mirror. When the current mirror M9, M10 action, I10 = 3I9. Similarly, when the current mirror M11, M12 action, I11 = 3I12. The width to length ratio of NMOS and PMOS dierential input transistor
satisfied W L
W L P
( ) ( ) =
µ µ
and I7 = I8 = Iref.
