Design of IP core of DPSK modulator with variable bit rate and carrier frequency based on FPGA

Dierential binary phase shift keying that is one of important digital modulations, is widely applied in modern communication for its featuring wide bandwidth utilization, strong anti-interference and eliminating the phase ambiguity. Because of the carrier frequency and bit rate of the current modulator in a market being changeless, there is a high error rate in the process of communication, when burst interference occurs in the communication channel. How to enhance the communication quality in that severe condition is very important. The paper describes a design schedule of FPGA-based based IP core of modulator with changed carrier frequency and bit rate, in which the carrier frequency and bit rate of the modulator are both adjusted to fit dierent communication environments. The modulator we designed features wide bandwidth utilization and low error rate.