ABSTRACT
Monolithic three-dimensional integrated circuit (3D-IC) is a vertical integration technology that builds and stacks two or more tiers of devices sequentially, rather than bonding two independently fabricated dies together using bumps and/or through-silicon vias (TSVs). Compared to other existing 3D integration technologies (wire-bonding, interposer, TSV, etc.), monolithic 3D integration allows ultrafine-grained vertical integration of devices and interconnects, thanks to the extremely small size of intertier vias, typically local-via-sized (50–100 nm in diameter).
In this chapter, we first study the manufacturing process of monolithic 3D-ICs. One of the crucial challenges here is the low-temperature process, as high temperatures used in the fabrication of the second tier may damage the metal layers of the first tier. Next, we review recent work on design and EDA (electronic design automation) tool development for monolithic 3D-IC technology targeting memory and logic applications. For monolithic 3D memory, we explore the static random-access memory (SRAM) design. In the case of digital logic, we explore three design styles. The first is transistor level, where individual logic gate is folded into multiple tiers. Second, we explore gate level, where individual gates occupy a single tier, but they are placed in multiple tiers and connected with intertier vias. The last design is block level, where individual IP blocks occupy a single tier and are connected with others in different tiers using intertier vias. We study the challenges and solutions for tier-to-tier performance variations, power and thermal considerations, and low-power design with respect to these design styles.
