ABSTRACT
Through-silicon-via (TSV) introduces new parasitic components into 3D ICs. They penetrate silicon substrate and are vulnerable to any signal noise through the substrate. They also introduce a large capacitance and affect the timing, power, and noise at the full-chip level. Thus, it is essential to extract TSV-related parasitics in detail to provide accurate signed-off timing and power analysis and verification. Due to the prohibitive time complexity involved in extracting parasitics from thousands of TSVs and millions of nets in a typical design, 3D-IC parasitic extraction has to be highly efficient while maintaining acceptable accuracy.
In this chapter, we model and extract two major types of TSV-related parasitics, namely, TSV-to-TSV and TSV-to-Wire coupling capacitance. TSV-to-TSV coupling, a major coupling element inside silicon substrate, can be modeled and calculated with mathematical equations. We also learn that various silicon-induced phenomena significantly affect the extraction results. TSV-to-Wire coupling, which is strongly depended on geometry structures, cannot be modeled by closed-form formulas easily. Thus, we learn a rule-based extraction, which is extended from the traditional 2D wire extraction. This method solves the computation problem with a good estimation accuracy. We also learn design optimization techniques that alleviate TSV-to-TSV and TSV-to-Wire coupling.
