ABSTRACT
A critical part of building a successful 3D system lies in the ability to physically arrange the circuitry in such a way that manages myriad complexities related to thermal management, wire length optimization, and communication overheads. This chapter first presents an overview of methods for 3D placement, both under TSV-based and monolithic integration models. Next, it discusses algorithms for 3D routing for gate-level design after placement. Finally, methods for optimized chip-level communication using 3D NoCs are discussed.
