Design Methodology for TSV-Based 3D Clock Networks

This chapter reviews the state-of-the-art design methodologies for TSV-based 3D clock networks and covers four ingredients: (1) the synthesis flows of basic 3D clock trees in comparison with the synthesis flow of 2D clock trees; (2) the importance of pre-bond testing and the support of pre-bond testability in 3D clock trees; (3) 3D clock tree design and synthesis techniques, which can tolerate clock TSV interconnect fault; (4) 3D clock tree synthesis algorithms, which can cope with various design variation parameters such as thermal variation, TSV-stress, on-package variation, and blockage awareness.