ABSTRACT
The generalized and programmable nature of FPGA has made them a popular choice for the implementation of digital circuits. However, the high flexibility of FPGAs makes them larger, slower and more power consuming than their counterpart ASICs [1]. This gap is due mainly to the FPGA interconnect network which is dominant factor in terms of area (until 90%) and power dissipation (65%). In order to remain attractive, FPGA fabric should offer a good trade-off between flexibility, performance and cost. These factors are linked to quality of the architecture, quality of the CAD tools and quality of the physical design. In this chapter, we tackle all these three points by proposing an efficient Tree-based architecture that unifies two unidirectional optimized programmable networks. We develop a new set of CAD tools to evaluate the architecture characteristics and to explore how to balance interconnect and logic utilization. Finally, we propose various 2D physical floor-planning techniques to manage layout feasibility, scalability and wire lengths issues. These techniques are extended to 3D integration to improve device density and performance.
