ABSTRACT
Interconnecting all the modules in an FPGA design is becoming ever more challenging, so this chapter examines how embedding a more structured, highlevel interconnect could reduce design effort and improve hardware efficiency. The chapter details what a Network-on-Chip (NoC) is and examines how an NoC can best be integrated into a new FPGA architecture. Key questions are how to keep the area cost of any new hardware added to the FPGA low, and how to maintain the flexibility of the FPGA to implement arbitrary designs when it contains a hardened NoC communication block. The chapter then determines how various design and communication styles can be mapped onto the embedded NoC, and examines the efficiency of several example designs in an NoC-enhanced FPGA.
