ABSTRACT
As the logic density of FPGAs steadily grows at Moore’s pace, design practices try to keep up with the increasing complexity, and possibly take advantage of it. One of the most natural trends is to raise the level of abstraction relying on already designed and engineered components (generally called Intellectual Properties, IPs), and instantiating and connecting them to team up towards the desired functionality. As the number of such components increases, the
and
communication between them becomes more relevant, and the design of the infrastructure to support it more sensible. Naive approaches such as pointto-point ad-hoc channels fail to scale, for at least two reasons: the quadratic growth in the number of endpoints affects not only obvious resources such as area and routing time (and cleverness) of the synthesis algorithm, but also effort of the designers, who have to devise adaptors between components exposing different interfaces and having different protocols.
