ABSTRACT
Fynn Schwiegelshohn, Philipp Wehner, Jones Mori Alves da Silva, Benedikt Janßen, Osvaldo Navaro Guzman, Jens Rettkowski, Muhammed Al Kadi, Diana Go¨hringer, and Michael Hu¨bner
Ruhr University Bochum, Bochum, DE
9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 9.2 Reconfigurable Hardware Architectures . . . . . . . . . . . . . . . . . . . . . . . . . 260
9.2.1 MPSoCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 9.2.2 NoCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 9.2.3 Processing Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
9.2.3.1 Reconfigurable Instruction Set . . . . . . . . . . . . . . . 264 9.2.3.2 Reconfigurable Computing Structures . . . . . . . 265 9.2.3.3 Reconfigurable Cache . . . . . . . . . . . . . . . . . . . . . . . . 271
9.2.4 Discussions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 9.3 Reconfigurable Architectures Management . . . . . . . . . . . . . . . . . . . . . . 276
9.3.1 Virtualization Technologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 9.3.1.1 Virtualization in Reconfigurable
Architectures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 9.3.1.2 Further Aspects of System Virtualization . . . 280
9.3.2 Scheduling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 9.3.3 Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
9.4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
Reconfigurability for single processors but also for multi-core architectures enables hardware and software adaptation to different requirements of applications and algorithms and allows finding an optimal point of operation in terms of performance and power. It is also exploitable at design time, e.g.,
and
by developing hardware and software according to a specification of a given application. However, in the best case, this reconfigurability is provided at runtime in order to react to requirements which were not predictable at design time. The increasing complexity of the hardware and the application scenarios need exactly such a system behavior in order to handle an infinite design space, which cannot be managed by the developers anymore. This chapter describes the opportunities of hardware (Section 9.2) and software (Section 9.3) adaptation at run-time on different levels.
