An Improved Programmable Neural Network and VLSI Architecture Using BiCMOS Building Blocks

A typical programmable neural network (PNN) implementation based on mixed analog/digital design have been proposed in [1]. In this paper, we analyze its basic circuits, including synapse and neuron, and improve their performance using BiCMOS technology. The corresponding PNN architecture in VLSI are developed and two kinds of building blocks, which are simpler since digital signals can be directly applied as programmable weights, are used in the architecture. Compared with the previous design, simulation results show that this PNN architecture can provide more accurate weight currents up to 30 times, and less silicon area and more driving capability by the factor of 2 and 3, respectively.