ABSTRACT
The progress of VLSI technologies is a result of an intimate interaction between improvements in IC chip design and in device properties of the underlying process technologies. The semiconductor roadmap following Moore’s law is responsible for an exponential decrease of minimum feature size of devices. The associated increase of device speed and decrease of supply voltage have strong implications for the available noise margin of a VLSI chip. This chapter addresses the main issues relevant for noise in VLSI technologies at various levels as indicated schematically in Fig. 9.1. At the microscopic level, the fundamental sources of noise associated with carrier transport are derived with emphasis on semiconductors. The next level deals with the noise properties of active devices and passive components. Three classes of active devices are chosen for illustration: bipolar junction transistors (BJTs), field effect transistors (FETs), and two terminal junction devices (diodes). Although the treatment of these device classes implies silicon-based technologies (Si-BJT, Si-MOSFET, Si-diode), it can generally be applied to other device classes as well (HBT, MESFET, etc.). Finally, the chip level noise is presented in terms of the major contributions being amplifier noise, oscillator noise, timing jitter, and interconnect noise. The evolution of VLSI technologies into the deep-sub-micron regime has significant implications for the treatment of fundamental noise mechanisms, which are briefly outlined in the last section of the chapter.
