ABSTRACT
Latchup is a destructive phenomenon that often results in blown bond wires and massive widespread destruction of the chip if the low-impedance path persists for long enough. Dimension scaling, higher integration levels and higher operating frequencies, all tend to aggravate latchup, so that aggressive control measures are required to avoid latchup in deep sub-micron products. Most often, latchup is triggered by some external effect, but the sensitivity to the latch may degrade over time through some intrinsic reliability mechanism. Therefore, latchup failures may be expected to occur anywhere in the bathtub curve. It is, however, possible to assess, in a qualitative way the component immunity to latchup through standard tests and/or procedures. There are several fundamental strategies for managing latchup: minimizing the probability of triggering latchup, maximizing circuit immunity to latchup triggers, and maximizing the holding voltage, that is, minimizing the circuit's ability to sustain a latch.
