ABSTRACT
Given that passive-matrix arrays exist and are slightly less expensive to fabricate than active-matrix arrays, it would be prudent to understand when a passive-matrix array design is suffi cient and when an active-matrix array design is necessary. Figures 5.1 and 5.2 show the electrical schematic and functional cross-sectional diagram of a passive matrix and an active matrix, respectively. It should be noted that the difference in passive-and active-matrix fabrication process costs has diminished in recent years due in a large part to the greater reduction in the number of processing levels for the active matrix as well as the realization of higher yields in manufacturing. It is not uncommon to fi nd a-Si TFT active-matrix manufacturers that employ a four-lithographic-step process with yields in the upper 90th percentile [1]. A passive-matrix array consists of two sets of electrically isolated conducting ITO bus lines (row and columns) arranged orthogonally to form the two LC-capacitorpixel electrodes at each intersection, and connected to integrated circuit drivers that supply the necessary voltage and timing sequence. Normally, the display is scanned or multiplexed row by row from the top to the bottom at a rate suffi cient to produce fl icker-free images (>60 Hz). The LC material follows the root mean square (rms) of the voltage over time.
